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3.3V SDRAM Modules 144 pin SO-DIMM SDRAM Modules 16MB, 32MB, 64MB & 128 MB density
HYS64Vx00(2)0G(C)D-10
* 144 Pin JEDEC Standard, 8 Byte Small Outline Dual-In-Line Synchronous DRAM Modules
for PC notebook applications
* One bank 2M x 64, 4M x 64, 8M x 64 and 16M x 64 non-parity module organisation * Two bank 16M x 64 organisation * Performance: -10 PC66 fCK tAC Clock frequency (max.) Clock access time CAS latency = 2 & 3 66 8 Units MHz ns
* Single +3.3V( 0.3V ) power supply * Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
* Auto Refresh (CBR) and Self Refresh * Decoupling capacitors mounted on substrate * All inputs, outputs are LVTTL compatible * Serial Presence Detect with E2PROM * 4096 refresh cycles every 64 ms * Gold contact pad * HYS64V8000GCD and HYS64V160(2)0GCD in COB techniques with 1" height only * This SDRAM product familiy is intended to be fully pin and architecture compatible with the 144
pin SO-DIMM DRAM module family.
Semiconductor Group
1
7.98
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
This SIEMENS module family are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use optional serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,5 mm long footprint. This module family is available in conventional and COB module assembly technique. Product Spectrum:
SDRAMs RowAddr. Bank Column Refresh used Select Addr. 8 2Mx8 11 BA0 9 4k 4 4Mx16 12 BA0, BA1 8 4k 8 8Mx8 12 BA0, BA1 9 4k 16 16Mx4 12 BA0,BA1 10 4k 16 8M x 8 12 BA0,BA1 9 4k Period 64 ms 64 ms 64 ms 64 ms 64 ms
2M x 64 4M x 64 8M x 64 16M x 64 16M x 64
HYS64V2000GD-10 HYS64V4000GD-10 HYS64V8000G(C)D-10 HYS64V1600GCD-10 HYS64V1620GCD-10
Card Dimensions:
Organisation 2M x 64 4M x 64 8M x 64 8M x 64 COB 16M x 64 COB PCB-Board L-DIM-144-6 L-DIM-144-7 L-DIM-144-8 L-DIM-144-C6 L-DIM-144-C7 L x H x T [mm] 67.60 x 25.40 x 3.80 67.60 x 25.40 x 3.80 67.60 x 31.75 x 3.80 67.60 x 25.40 x 3.80 67.60 x 25.40 x 3.80
Pin Names
A0-A10 A0-A11 BA0 BA0,BA1 DQ0 - DQ63 RAS CAS WE CKE0 CLK0 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. Address Inputs for 2M x 64 modules Address Inputs for 4M x 64, 8M x 64 & 16M x 64 modules Bank Select for 2M x 64 modules Bank Selects for 4M x 64, 8M x 64& 16M x 64 modules Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection
Semiconductor Group
2
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
Pin Configuration
PIN # Front Side VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC CKL0 Vcc RAS WE CS0 NC ( CS1) PIN # Back Side VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc CAS CKE1 (A12) (A13) PIN # Front Side NC Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc PIN # Back Side CKL1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
Semiconductor Group
3
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
WE CS0 DQMB0 DQ0-DQ7 CS WE DQM DQ0-DQ7 D0 CS WE DQMB1 DQ8-DQ15 DQM DQ0-DQ7 D1 DQMB5 DQ40-DQ47 DQM DQ0-DQ7 D5 DQMB4 DQ32-DQ39 DQM DQ0-DQ7 D4 CS WE CS WE
DQMB2 DQ16-DQ23
CS WE DQM DQ0-DQ7 D2 CS WE DQMB6 DQ48-DQ55 DQM
CS WE DQ0-DQ7 D6 CS WE DQMB7 DQ56-DQ63 DQM DQ0-DQ7 D7
DQMB3 DQ24-DQ31
DQM DQ0-DQ7 D3
A0-A10, BA0 VCC
D0 - D7 D0 - D7 C1-C8 D0 - D7 D0 - D7 D0 - D7 D0 - D7
E2PROM (256wordx8bit) SA0 SA1 SA2
VSS RAS CAS CKE0
SCL SDA
CLK0 CLK1
D0, D1 D4,D5 D2, D3 D6,D7
Note: all resistor values are 10 Ohms
Block DIagram for 2M x 64 SDRAM - DIMM module
Semiconductor Group
4
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
WE CS0 CS WE DQMB0 DQ0-DQ7 DQMB1 DQ8-DQ15 LDQM DQ0-DQ7 UDQM DQ8-DQ15 D0 DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 LDQM DQ0-DQ7 UDQM DQ8-DQ15 D2 CS WE
CS WE DQMB2 DQ16-DQ23 DQMB3 DQ24-DQ31 LDQM DQ0-DQ7 UDQM DQ8-DQ15 D1 DQMB6 DQ48-DQ55 DQMB7 DQ56-DQ63 LDQM
CS WE
DQ0-DQ7 UDQM DQ8-DQ15 D3
A0-A11, BA0, BA1 VCC C1-C4 VSS RAS CAS CKE0 CLK0 CLK1
D0 - D3 D0 - D3 D0 - D3 D0 - D3 D0 - D3 D0 - D3 D0, D2 D1, D3
10 pF
E2PROM (256wordx8bit) SA0 SA1 SA2
SCL SDA
note: all resistors are 10 Ohms
Block DIagram for 4M x 64 SDRAM - DIMM module
Semiconductor Group
5
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
WE CS0 DQMB0 DQ0-DQ7 CS WE DQM DQ0-DQ7 D0 CS WE DQMB1 DQ8-DQ15 DQM DQ0-DQ7 D1 DQMB5 DQ40-DQ47 DQM DQ0-DQ7 D5 DQMB4 DQ32-DQ39 DQM DQ0-DQ7 D4 CS WE CS WE
DQMB2 DQ16-DQ23
CS WE DQM DQ0-DQ7 D2 CS WE DQMB6 DQ48-DQ55 DQM
CS WE DQ0-DQ7 D6 CS WE DQMB7 DQ56-DQ63 DQM DQ0-DQ7 D7
DQMB3 DQ24-DQ31
DQM DQ0-DQ7 D3
A0-A11, BA0,BA1 VCC C1-C8 VSS RAS CAS CKE0 D0 - D7 D0 - D7 D0 - D7
D0 - D7 D0 - D7 D0 - D7
E2PROM (256wordx8bit) SA0 SA1 SA2
SCL SDA
CLK0 CLK1
D0, D1 D4,D5 D2, D3 D6,D7
Note: all resistor values are 10 Ohms
Block Diagram for 8M x 64 SDRAM DIMM - Module
Semiconductor Group
6
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
CS0 DQMB0 DQM CS DQ0-DQ3 DQ0-DQ3 DQM CS DQ4-DQ7 DQMB1 DQM CS DQ8-DQ11 DQ0-DQ3 DQM CS DQ12-DQ15 DQMB2 DQM CS DQ16-DQ19 DQ0-DQ3 DQM CS DQ20-DQ23 DQMB3 DQM CS DQ24-DQ27 DQ0-DQ3 DQM CS DQ28-DQ31 DQ0-DQ3 D7 D6 DQ0-DQ3 D4 DQ0-DQ3 D3 D2 DQ0-DQ3 D0
DQMB4 DQ32-DQ35
DQM CS DQ0-DQ3 DQM CS D8
DQ36-DQ39 D1 DQMB5
DQ0-DQ3 DQM CS
D9
DQ40-DQ43
DQ0-DQ3 DQM CS
D10
DQ44-DQ47 DQMB6 DQ48-DQ51
DQ0-DQ3 DQM CS DQ0-DQ3 DQM CS
D11
D12
DQ52-DQ55 D5 DQMB7
DQ0-DQ3 DQM CS
D13
DQ56-DQ59
DQ0-DQ3
D14
DQM CS WE DQ61-DQ63 DQ0-DQ3 D15
E2PROM (256wordx8bit) D0 - D15 D0 - D15 C D0 - D15 D0 - D15 16 SDRAMS Clock Wiring 16M x 64 CLK0 8 SDRAMS CLK1 8 SDRAMS
10 10
A0-A11,BA0,BA1 VDD VSS
SA0 SA1 SA2
SCL SDA
RAS, CAS, WE CKE0
Note: DQ wiring may differ than describes in this drawing, however DQ/DQMB/CKE/CS relationship must be maintained as shown.
4 SDRAMs 4 SDRAMs
CK0
Block Diagram for one bank 16M x 64 SDRAM DIMM - Module (16M x 4 based)
Semiconductor Group
7
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
CS1 CS0 CS DQMB0 DQ(7:0) DQM DQ0-DQ7 D0 CS DQMB1 DQ(15:8) DQM DQ0-DQ7 D1 CS DQMB2 DQ(23:16) DQM DQ0-DQ7 D2 CS DQMB3 DQ(31:24) DQM DQ0-DQ7 D3 D0 - D15 E2PROM (256wordx8bit) D0 - D15 C D0 - D15 D0 - D15 D0 - D7 D8 - D15 SA0 SA1 SA2 DQM DQ0-DQ7 D11 DQM DQ0-DQ7 D10 CS DQMB7 DQ(63:56) DQM DQ0-DQ7 D7 DQM DQ0-DQ7 D9 CS DQMB6 DQ(55:48) DQM DQ0-DQ7 D6 CS DQM DQ0-DQ7 D15 DQM DQ0-DQ7 D8 CS DQMB5 DQ(47:40) DQM DQ0-DQ7 D5 CS DQM DQ0-DQ7 D14 CS CS DQMB4 DQ(39:32) DQM DQ0-DQ7 D4 CS DQM DQ0-DQ7 D13 CS CS DQM DQ0-DQ7 D12 CS CS
A0-A11,BA0,BA1 VDD VSS
RAS, CAS, WE CKE0 CKE1
SCL SDA
Clock Wiring 16M x 64 CLK0 8 SDRAM CLK1 8 SDRAM
4 SDRAMs CK0 4 SDRAMs Note: DQ wiring may differ than describes in this drawing, however DQ/DQMB/CKE/CS relationship must be maintained as shown.
Block Diagram for two bank 16M x 64 SDRAM DIMM - Module ( 8M x 8 based)
Semiconductor Group
8
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
DC Characteristics TA = 0 to 70 VSS = 0 V; VDD,V DDQ = 3.3 V 0.3 V C; Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Symbol Limit Values min. max. Vcc+0.3 0.8 - 0.4 20 20 V V V V A A 2.0 - 0.5 2.4 - - 20 - 20 Unit
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 VDD = 3.3 V 0.3 V, f = 1 MHz C; Parameter Symbol Limit Values 2M x 64 4M x 64 8M x 64 16Mx 64 max. max. max. max. Input capacitance (A0 to A11, BA0, BA1) Input capacitance (RAS, CAS, WE, CKE0) Input Capacitance (CLK0, CLK1) Input capacitance (CS0) Input capacitance (DQMB0-DQMB7) Input / Output capacitance (DQ0-DQ63) Input Capacitance (SCL,SA0-2) Input/Output Capacitance Unit
CI1 CI2 CI3 CI4 CI5 CIO
Csc Csd
18 18 25 18 7 8 8 10
45 50 45 45 10 9 8 10
pF pF pF pF pF pF pF pF
Semiconductor Group
9
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
AC Characteristics 1)2) TA = 0 to 70 VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns C; Parameter
Symbol
Limit Values -10 min. max.
Unit
Note
Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System Frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall) Common Parameters RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank) Refresh Cycle Self Refresh Exit Time Refresh Period (4096 cycles)
tCK
10 15 ns ns 100 66 8 8 - - - - - - - MHz MHz ns ns ns ns ns ns ns ns ns
2, 4,
fCK
- -
tAC
- -
tCH tCL tCS tCH tCKSP tCKSR tT
3 3 3 1 3 8 1
6 6 7 7 8 9
tRCD tRC tRAS tRP tRRD tCCD
30
75
- - - - - -
ns ns ns ns ns CLK
2 CLK 7 CLK 3 CLK 2 CLK 1 CLK
45 30 20 1
tSREX tREF
2CLK +tRC - 64
ns ms
9) 8)
Semiconductor Group
10
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
Parameter
Symbol
Limit Values -10 min. max.
Unit
Note
Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency Write Cycle Data Inut to Precharge (write recovery) Data In to Active / Refresh DQM Write Mask Latency
tOH tLZ tHZ tDQZ
3 0 3 2
- - 10
ns ns ns CLK
2, 4
10
tWR tDAL tDQW
2 5
- - -
CLK CLK CLK
0
Semiconductor Group
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HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
Notes: 1. An initial pause of 100s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shown.Specified tac and toh parameters are measured with a 50
2.4 V CLOCK 0.4 V
+ 1.4 V 50 Ohm Z=50 Ohm
tT
tSETUP tHOLD
INPUT
1.4V
I/O 50 pF
tAC tLZ tOH
tAC
I/O 50 pF
OUTPUT
1.4V
Measurement conditions for tac and toh
tHZ
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. 3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to " wake-up"the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 8. tDAL is equivalent to tDPL + tRP. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
Semiconductor Group
12
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
Serial Presence Detects:
A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus)
SPD-Table:
Byte# Description SPD Entry Value 2Mx64 -10 80 08 04 0B 09 01 40 00 01 A0 80 00 80 08 00 01 8F 02 06 01 01 00 06 F0 80 FF FF 1E 4Mx64 -10 80 08 04 0C 08 01 40 00 01 A0 80 00 80 10 00 01 8F 04 06 01 01 00 06 F0 80 FF FF 1E Hex 8Mx64 16Mx64 16Mx64 -10 -10 -10 80 80 80 08 08 08 04 04 04 0C 0C 0C 09 01 40 00 01 A0 80 00 80 08 00 01 8F 04 06 01 01 00 06 F0 80 FF FF 1E 09 02 40 00 01 A0 80 00 80 08 00 01 8F 04 06 01 01 00 06 F0 80 FF FF 1E 0A 01 40 00 01 A0 80 00 80 04 00 01 8F 04 06 01 01 00 06 F0 80 FF FF 1E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont' d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-toback random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time
128 256 SDRAM
1 64 0 LVTTL 10.0 ns 8.0 ns none Self-Refresh, 15.6s n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full page 2 2, & 3 CS latency = 0 Write latency =0 non buffered/ non reg. Vcc tol +/10% 15.0 ns 8.0 ns not supported not supported 30 ns
Semiconductor Group
13
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
SPD-Table (cont' d):
Byte# Description SPD Entry Value 2Mx64 -10 14 1E 2D 04 30 10 30 10 FF 12 91 FF 66 C7 FF 4Mx64 -10 14 1E 2D 08 25 10 25 10 FF 12 89 FF 66 87 FF Hex 8Mx64 16Mx64 16Mx64 -10 -10 -10 14 14 14 1E 2D 10 25 10 25 10 FF 12 8A FF 66 C7 FF 1E 2D 10 25 10 25 10 FF 12 8B FF 66 C7 FF 1E 2D 20 25 10 25 10 FF 12 97 FF 66 C7 FF
Minimum Row Active to Row Active delay 29 Minimum RAS to CAS delay 30 Minimum Ras pulse width 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures' information (optional) s 125 126 Frequency Specification 127 Details 128+ Unused storage locations
28
20 ns 30 ns 45 ns 3 ns 1 ns 3 ns 1 ns Revision 1.2
PC66
Semiconductor Group
14
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
L-DIM-144-6 16 MByte SO-DIMM Module package (144 pin, dual read-out, single in-line memory module)
Front Side:
67,5 63,6 3,8
4,0
6,0
1 3,3 23.2 24.5
59
61 32.8 4,6 2,5
143
20,0
25,40
1.0 +0.1 -
Backside: 3,7 2 60
O 1,8 62 144
Detail of Contacts: 0.25 max 2.54 min
Details of Notch : 1,5 +/-0,1 4,0 +/-0,1
2Mx64 SDRAM SODIMM DM144-6.WMF
0,8
0,6+/- 0.05
preliminary drawing
Semiconductor Group
15
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
L-DIM-144-7 32 MByte SO-DIMM Module package (144 pin, dual read-out, single in-line memory module)
Front Side:
67,5 63,6 3,8
4,0
6,0
1 3,3 23.2 24.5
59
61 32.8 4,6 2,5
143
20,0
25,40
1.0 +0.1 -
Backside: 3,7 2 60
O 1,8 62 144
Detail of Contacts: 0.25 max 2.54 min
Details of Notch : 1,5 +/-0,1 4,0 +/-0,1
4Mx64 SDRAM SODIMM
DM144-7.WMF
0,8
0,6 +/- 0.05
preliminary drawing
Semiconductor Group
16
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
L-DIM-144-8 64 MByte SO-DIMM Module package (144 pin, dual read-out, single in-line memory module)
Front Side: 67,5 63,6 3,8
4,0
6,0
1 3,3 23.2 24.5
59
61 32.8 4,6 2,5
143
20,0
31,75
1.0 +0.1 -
Backside: 3,7 2 60
O 1,8 62 144
Detail of Contacts: 0.25 max 2.54 min
Details of Notch : 1,5 +/-0,1 4,0 +/-0,1 8Mx64 SDRAM SODIMM
DM144-8.WMF
0,8
0,6+/- 0.05
preliminary drawing
Semiconductor Group
17
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
L-DIM-144-C6 64 MByte COB SO-DIMM Module package (144 pin, dual read-out, single in-line memory module)
Front Side: 67,5 63,6 3,8
4,0
6,0
1 3,3 23.2 24.5
59
61 32.8 4,6 2,5
143
20,0
25,40
1.0 +0.1 -
Backside: 3,7 2 60
O 1,8 62 144
Detail of Contacts: 0.25 max 2.54 min
Details of Notch : 1,5 +/-0,1 4,0 +/-0,1
8Mx64 COB-SDRAM SODIMM DM144-C6.WMF
0,8
0,6+/- 0.05
preliminary drawing
Semiconductor Group
18
HYS64Vx00(2)0G(C)D-10 144 pin SO-DIMM SDRAM Modules
L-DIM-144-C7 128 MByte COB SO-DIMM Module package (144 pin, dual read-out, single in-line memory module)
Front Side: 67,5 63,6 3,8
4,0
6,0
1 3,3 23.2 24.5
59
61 32.8 4,6 2,5
143
20,0
25,40
1.0 +0.1 -
Backside: 3,7 2 60
O 1,8 62 144
Detail of Contacts: 0.25 max 2.54 min
Details of Notch : 1,5 +/-0,1 4,0 +/-0,1
16Mx64 COB-SDRAM SODIMM DM144-C7.WMF
0,8
0,6 +/- 0.05
preliminary drawing
Semiconductor Group
19

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